1. Field of the Invention
The present invention relates in general to a write driver circuit with a write-per-bit (referred to hereinafter as WPB) data masking function, and more particularly to a write driver circuit for performing a WPB data masking operation instead of a data input buffer so that a WPB operation can be accomplished at high speed.
2. Description of the Prior Art
Generally, a WPB data masking operation is performed in a memory device with a large number of banks. The execution of the WPB data masking operation is determined according to the input of a row active command and enabled according to the input of a column active command.
In other words, because the WPB data masking operation is performed by an input buffer of the memory device and a plurality of memory banks share the input buffer, the enabling of the WPB data masking operation is determined according to which one of the banks is made column-active.
FIG. 1 is a circuit diagram of a conventional input buffer with a WPB data masking function. As shown in this drawing, the input buffer comprises an input unit 1 for inputting data IN to be written in a memory cell, through an input pad, first and second delay circuits 2 and 3 for delaying output data from the input unit 1, respectively, a first latch circuit 4 for latching output data /din from the first delay circuit 2 in response to a load column register enable signal lcr, a second latch circuit 5 for latching the output data /din from the first delay circuit 2 in response to a load masking register enable signal lmr, an output unit 6 for transferring output data from the second delay circuit 3 and first latch circuit 4 to a write driver circuit (not shown), and an output controller 7 for controlling the output of the output unit 6 in response to an output signal from the second latch circuit 5 and a WPB signal. The output controller 7 includes an inverter for inverting the WPB signal, and a NOR gate for NORing the output signal from the second latch circuit 5 and an output signal /WPB from the inverter. The write driver circuit is adapted to write output data from the output unit 6 in a memory cell in response to a normal data/block write data output enable signal (not shown).
The operation of the input buffer with the above-mentioned construction will hereinafter be described.
If data to be written is inputted through the input pad, then it is delayed by the first and second delay circuits 2 and 3, respectively. The output data din from the second delay circuit 3 is transferred as normal write data to the write driver circuit through the output unit 6. The output data /din from the first delay circuit 2 is latched by the first and second latch circuits 4 and 5, respectively, in response to the load column register enable signal lcr and load masking register enable signal lmr and then transferred as block write data to the write driver circuit through the output unit 6.
At this time, the output data from the output unit 6 is transferred or blocked to the write driver circuit according to a state of an output signal from the NOR gate in the output controller 7.
Namely, in the case where data to be masked is present, the WPB signal is enabled high in logic and then inverted into low in logic by the inverter. The low logic signal from the inverter is applied to one input terminal of the NOR gate, the other input terminal of which is applied with the output signal from the second latch circuit 5 which is low in logic.
As a result, the output signal from the NOR gate becomes high in logic to turn off output terminals of the output unit 6. Thereafter, when the masking operation is required to be released, the WPB signal is disabled low in logic so that the normal write operation can be performed.
As mentioned above, the conventional WPB data masking operation is performed by the input buffer to mask the data input to the write driver circuit. To this end, the conventional WPB data masking operation should be executed when the column active signal is inputted.
For this reason, which one of the banks made column-active must inevitably be determined at the initial clock of the WPB operation. Such a determination step delays the write execution, resulting in the formation of a critical path.